The present invention relates to a semiconductor device and a method of manufacturing the device. More particularly, it relates to a semiconductor device comprising gate oxide films and/or gate electrodes formed on the same substrate, made of different materials and/or being different in thickness, and also to a method of manufacturing this semiconductor device.
Hitherto, the transistors incorporated in an LSI (Large-scale Integration) circuit device such as a DRAM (Dynamic Random Access Memory) have a gate insulator film having a uniform thickness in most cases. LSIs incorporating transistors having such a gate insulator film are advantageous in two respects. First, they can be manufactured by a simple method and, hence, at low cost. Second, they can be manufactured with a high yield. However, they have but low operating efficiency, inevitably because they can not incorporate high-speed transistors recently developed.
In recent years, it is required that two types of gate insulator films or gate electrodes be formed on the same substrate. This is because, in the case where two or more different power-supply voltages are applied in the circuits formed in the same semiconductor substrate, the gate insulator films of the transistors provided in a high-voltage circuit section must be thick to render the circuit section reliable. For example, the gate insulator films of the transistors incorporated in DRAM or EPROM (Electrically Erasable and Programmable Read-Only Memory) cells are made thicker than the gate insulator films of the other circuit sections.
Most CMOS (Complementary Metal Oxide Semiconductor) circuits hitherto made include n+ polysilicon gates. To have a threshold voltage of PMOS (P-channel MOS) transistor controlled appropriately, each PMOS transistor has so-called buried channel structure. With this element structure it has become difficult to suppress the short-channel effect of the PMOS transistor. In this respect, a so-called dual-gate structure is considered in PMOS more desirable than the buried channel structure.
In a CMOS circuit of the dual-gate structure, the gate electrode of each PMOS transistor is made of p+ polysilicon, and the gate electrode of each NMOS (N-channel MOS) transistor is made of n+ polysilicon. The circuit of the dual-gate structure can operate more efficiently, if the gate insulator films differ in thickness.
Generally, a surface region of the substrate is divided into two regions by means of photolithography in preparation for forming two types of gate insulator films or gate electrodes on the same substrate. An example will be described below.
After forming a trench isolation in the surface region of a semiconductor substrate, a thermal oxide film is formed on the substrate by means of thermal oxidation. Next, a photoresist is coated on the entire surface of the substrate. That part of the photoresist in which a PMOS region is formed, is removed; the photoresist remains on only an NMOS region. Using the photoresist thus patterned as a mask, that part of the thermal oxide film, which is formed on the PMOS region, is removed by etching. Further, the photoresist is removed from the NMOS region, and thermal oxidation is performed on the substrate again, thereby forming a thermal oxide film on the entire upper surface of the resultant structure. Since the thermal oxide film formed by the first thermal oxidation remain on the NMOS region, the NMOS region is now covered with a thicker oxide film than the PMOS region.
In the process described above, however, the gate oxide film on the NMOS region directly contacts the photoresist. The photoresist contains much impurities, such as Na and heavy metals, which deteriorate the quality of the gate insulator film provided on the NMOS region. The impurities may diffuse into the gate oxide film formed on the NMOS in the following oxidation steps. If so, the reliability and yield of the element formed in the NMOS region are decreased.
Another method of manufacturing a conventional semiconductor device will be described, with reference to FIG. 1, FIGS. 2A to 2F, and FIGS. 3A to 3E.
FIG. 1 is a schematic plan view of a conventional semiconductor device. As shown in FIG. 1, the device comprises an trench isolation 1, a gate wiring region 2, and diffusion regions 3a and 3b. A first transistor is provided on the diffusion region 3a, and a second transistor on the diffusion region 3b. The gate insulator films of these transistors are made of different materials and/or have different thicknesses. The gate electrodes of these transistors are made of different materials and/or have different thicknesses.
FIGS. 2A to 2F are sectional views, each consisting of a right section and a left section, taken along line IIa--IIa and line IIb--IIb in FIG. 1, respectively. In other words, FIGS. 2A to 2F are sectional views explaining the steps of manufacturing the first transistor in the right sections, and the steps of manufacturing the second transistor in the left sections. FIGS. 3A to 3E are sectional views, all taken along line III--III in FIG. 1.
At first, a well region (not shown) and an isolation 11 of STI (Shallow Trench Isolation) structure are formed in a silicon substrate 10. Thereafter, a first gate oxide film 12 is formed on the substrate 10 by means of thermal oxidation. A polysilicon film 13, which will be processed into a first gate electrode, is formed on the first gate oxide film 12 by means of a CVD (Chemical Vapor Deposition) method. Dopant impurities are added to the polysilicon film 13 while the film 13 is being formed, or ion-implanted into the film 13 after the film 13 has been formed (see FIGS. 2A and 3A).
Next, the polysilicon film 13 is patterned by means of lithography and dry etching, forming a pattern covering only the region in which the first transistor will be formed. Diluted hydrofluoric acid solution is applied to that part of the first gate oxide film 12 which is exposed. As a result, this part of the film 12 is etched away, exposing a part of the silicon substrate 10 (see FIGS. 2B and 3B).
A second gate insulator film 14 is formed on the parts, thus exposed, of the silicon substrate 10 by means of thermal oxidation. At the same time, the top and sides of the polysilicon film 13, i.e., the first gate electrodes, are also oxidized. Hence, the silicon oxide film 14 covers the top and sides of the polysilicon film 13, as well as the exposed parts of the substrate 10. A polysilicon film 15, i.e., the second gate electrode, is formed on the silicon oxide film 14 by means of CVD method (see FIGS. 2C and 3C).
Thereafter, the second polysilicon film 15 is patterned, by means of lithography and dry etching, forming a pattern covering only the region in which the second transistor will be formed. Diluted hydrofluoric acid solution is applied to that part of the second gate oxide film 14 which is exposed. As a result, this part of the film 14 is etched away, exposing a part of the silicon substrate 10 (see FIGS. 2D and 3D).
A tungsten silicide (WSi.sub.2) film 16 is formed on the entire upper surface of the resultant structure (see FIGS. 2E and 3E). The film 16 will be processed into a third gate electrode which connects the first and second gate electrodes.
Next, the tungsten silicide film 16 and the polysilicon films (first and second gate electrodes) are processed into gate wires by means of lithography and dry etching (see FIGS. 2F and 3E).
Thereafter, steps of ordinary types, such as post oxidation, remaining side walls, forming of sources and drains and metalization, are carried out. The first and second transistors are thereby formed, which have gate oxide films different in thickness.
The semiconductor integrated circuit manufactured by the conventional method described above is disadvantageous in the following respects.
First, the first gate electrode 13 and the second gate electrode 15 must be overlapped at the junction for a distance W, as shown in FIG. 3E, due to the insufficient alignment margin available in the photolithography. The channel regions of the transistors, which are active regions, must be spaced away from the junction of the gate electrodes 13 and 15. Hence, the trench isolation is inevitably broad by the distance W for which the gate electrodes 13 and 15 overlap at the junction. This results in an increase in the size of the whole device, a reduction in the number of chips that can be cut from one silicon wafer, and ultimately in an increase in the manufacturing cost of the semiconductor integrated circuit device.
Second, the surface of the semiconductor integrated circuit (the tungsten silicide (WSi.sub.2) film 16) is not flat and has different heights, as shown in FIG. 3E. This complicates the lithography and dry etching that are carried out to form the gate wires. It would be difficult for the semiconductor integrated circuit device to have elements which are as small as is designed.